The process for producing an integrated circuit comprises many steps. Conventionally, a logic design is followed by a circuit design, which is followed by a layout design. With respect to the circuit design and layout portion, once circuits for an integrated circuit have been designed, such designs are converted to a physical representation known as a “circuit layout” or “layout.” Conventionally, a layout may be viewed as an elevational view representing semiconductor process layers forming physical devices, such as transistors, contacts, and buses, among other well-known circuit elements. Layout is exceptionally important to developing a working design as it affects many aspects, including, but not limited to, signal noise, signal time delay, resistance, cell area, and parasitic effect.
Once an initial layout is done, it must be checked to ensure spacing between circuit elements conforms to a set of rules known as Design Rules. Design Rules conventionally set minimum spacings, sizes and the like for circuit elements. Though a layout is developed with such Design Rules in mind, there may be violations of such Design Rules owing to complexity or magnitude of the circuitry to be laid out or of the Design Rules themselves.
Accordingly, a next step in the design process is to perform a Design Rule Check, more commonly known as a DRC, on a layout. This step is important because violation of one or more Design Rules may result in a higher probability, and in some cases an absolute certainty, that a fabricated chip would not work as desired.
Conventionally, a circuit designer designs a circuit on a computer using a computer-aided design (CAD) tool. Data from such a CAD designed circuit is provided to a computer-aided engineering (CAE) tool. This CAE tool is used to produce a layout. However, a layout so produced may still have one or more Design Rule violations. Accordingly, what is known as “Physical Verification and Analysis” is done. Components of this include a DRC and a Layout Versus Schematic (LVS) check. DRC and LVS are conventionally done with a Design Rule Checker and an LVS Verifier, both of which are CAE tools.
A Design Rule Checker may access specified Rules File and Rules Library for purposes of checking a proposed layout. Unfortunately, Rules Files, or DRC files, conventionally are written with numbers associated with logical operators embedded in such files. Moreover, it is not uncommon for a same number to be used multiple times throughout a file. However, though a number may appear in multiple places does not necessarily mean it refers to the same rule. This makes update DRC file numbers time consuming and prone to error.
Accordingly, it would be desirable to provide DRC file updating solution that is less time intensive and error prone.
Furthermore, there are additional EDA tools which use “technology files” that contain design rule information. These technology files are used to control and configure EDA tools. Some examples of EDA tools which require technology files containing design rule data are extraction, compaction, and parameterized cells layout.